Greg LaBonte ,Software Product Manager, Test Advantage.  Today, electronic systems account for more than 20 percent of the value of a new automobile, and that figure is expected to increase to more than 40 percent by 2010 . The desire to increase reliability in this competitive marketplace, along with ensuring that safety liabilities are under control, have acted as significant catalysts for automotive device manufacturers to aggressively pursue “Zero Defect” semiconductor device manufacturing strategies.

     1. Outlier Detection – The identification of quality risk devices within the passing devices population

“History has shown that parts with abnormal characteristics significantly contribute to quality and reliability problems.” This quote is taken directly out of the Automotive Electronics Council’s AEC-Q001 guideline, first published in 1997, which defined a concept for Part Average Testing (PAT). This was the first step in attempting to standardize a production strategy for identifying quality risk devices within the passing devices population. Semiconductor integrated device manufacturers supplying components to high reliability markets, such as the automotive industry, have been directly influenced to adopt PAT concepts for the identification and removal of device “Outliers” in the attempt to reduce Defective Parts Per Million (DPPM) rates.

Over the years, due to the lack of commercially available solutions, the semiconductor device supply base has pursued various methodologies consistent with PAT in order to identify and remove device quality risks during the manufacturing and test processes which simply fall short of being efficient, comprehensive, cost-effective or easy-to-implement within the production environment.

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STMicroelectronics and Test Advantage jointly present the integration and demonstrated performance of a post wafer sort, test data analysis system for reduced DPPM. This discussion will outline the complete solution of all the key elements coming together as a fully automated manufacturing process referred at the semiconductor supplier level as the Automotive Grade Program.

This program comprehends reduction of intrinsic defects at design using techniques that define solutions for robustness validation during new products development, and embodies techniques for identifying extrinsic defects through the application of advanced outlier detection screening methods to eliminate parts that pose a quality risk.

The presentation will focus on the advanced outlier detection implementation and explore how both companies framed the project using core competencies from within both organizations. The semiconductor supplier has provided the integration platform, functional requirements and the overall program management support and leadership. The solution provider has delivered a state of the art capability for data analysis, utilizing an adaptive algorithms selection methodology based upon test data distribution shapes. This effort also involved the delivery of support during tool integration at the wafer-sort test facilities involving both training and consultancy.

Executive commitment from both companies was evident throughout the project with the active role of an executive council and a technical committee targeting the achievement of program objectives without production interruption. Direct and lateral benefits of the program are examined identifying related risks along with solutions to control these risks.

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Historically it has been proven that post processing of sort test data is the most effective way of identifying outlier devices, since this gives the most accurate and comprehensive view of parametric and spatial characteristics. However, any form of data analysis aimed at DPPM improvement is inherently dependent on the quality or integrity of the data being analyzed. Before exploring the concepts of maximizing the effectiveness of the post data analysis, you must first analyze the test environment to ensure that the data produced at sort for outlier detection is in fact optimized to represent the performance of the device, and is free from second-order effects caused by non-ideal aspects of the test process. These include, for example, multimodal distributions as a result of site-to-site variation, which will limit the effectiveness of outlier detection techniques. The presence of tester alarms or poor result resolution may be indications of incorrect setup for a given test. Incorrect test limit settings can affect outlier detection, which is normally performed on the Bin1 population. There are many other indications of potential problems either in the setup or measurement aspects of a given test, which can have a negative impact on the effectiveness of DPPM reduction, and should result in some form of corrective action. The outcome of this corrective action should actually have a positive impact on the overall testing process, improving the quality of the data generated, and perhaps even addressing causes of yield reduction during testing.

Additionally, a comprehensive analysis of the test environment itself, through interpretation of the data it produces, can give valuable insights into maximizing the efficiency of the post test data analysis in the production environment. Tests that exhibit a higher outlier density can be identified and given special consideration. Highly correlated pairs of tests can be identified as good candidates for linear-regression based detection techniques, which allow identification of outliers within the main population which do not conform to the underlying relationship between the two datasets.

Manual identification of these corrective actions, and tests that can play a key role in maximizing

DPPM reduction efficiency, is a lengthy, tedious and error-prone process. Automating the data analysis effort provides the obvious benefit of allowing the analysis of all the data regardless of magnitude. It is clear that a standardization of automated test data analysis is an effective leveling opportunity to ensure department compliance to desired programming quality standards and will significantly reduce test program development time. An automated, user-configurable framework will be described that can achieve these goals, quickly and in a repeatable manner.

It is recognized that each wafer represents a unique processing demographic as a result of modern wafer fabrication processing methods. Post-processing of sort test data using adaptive outlier detection techniques analyze the data on a per-wafer, per-test basis. This methodology comprehends any type of data population distribution and applies the appropriate detection algorithms. Quality risk devices are then determined based on user defined classification logic accumulating both magnitude and frequency of the identified anomalies across all parametric tests.

This defined framework of automated test program data analysis is then highly leveraged with adaptive automated in-line outlier detection, increasing test efficiencies and improving overall manufacturing yield while reducing DPPM.

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PAT as a tool for outlier detection is an established technique for improving reliability. The basic PAT methodology is designed for (parametric) test data populations that have a Gaussian distribution. In practice, however many test data populations do not meet these criteria, restricting the application of the PAT algorithm.

This presentation will describe a fully automated system for the implementation of outlier detection at EWS (electrical wafer sort). By building on the strengths of PAT and incorporating enhancements that permit the application of outlier detection to a much wider range of data distributions, the system can analyze all parametric test results on a per wafer basis, selecting the most appropriate detection algorithm for each test based on the population distribution encountered. Once complete, the results of the analysis are used to update the prober ink map to remove any outlier parts that have been identified.

The system implements several novel techniques to enhance the detection process. First, a custom algorithm has been developed that analyzes the test results in context with the associated test limits, identifying ‘test outliers’ rather than conventional distribution outliers. The outlier results are then classified based on the magnitude of the result (with respect to the main population), greater significance being attributed to larger outliers. To conclude the analysis, a device-orientated approach is adopted; such that by looking at the outlier results for each x, y, location on a wafer, the presence of multiple outliers allows the identification of outlier devices rather than simply test result outliers.

Finally, in addition to parametric outliers, analysis of probe test data permits geographic (spatial) outliers or ‘good die in a bad neighborhood’ to also be included in the analysis.

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The data routinely collected as part of the manufacturing process contains many hidden treasures that can greatly benefit the overall manufacturing process. These benefits include, but are not limited to, DPPM reduction, yield improvement, throughput improvement, time-to-market reduction, and lowering of the overall cost-of-test.

However, the time and effort required to realize these benefits means that they are frequently sacrificed, and detailed data analysis is performed on an "exception-only" basis, in response to a yield bust, for example.

Beyond the time and effort investment, other analysis technology barriers have historically prevented the taking of full-advantage of these hidden treasures. For example, analysis has to be robust and tolerant to the presence of outliers, and adaptive to changing distributions and trends. It has to be able to take account of the non-ideal aspects of any manufacturing process. Frequently, it has to be performed real-time, especially in the case of DPPM reduction within a production environment. It has to be flexible, to meet the differing needs of different product groups and markets; automated, requiring a minimum of human intervention, and it has to integrate smoothly with existing manufacturing processes.

This paper will detail an analysis framework that can realize all of these goals, in a scalable fashion. This framework has been successfully demonstrated on a wide range of data, and new features continually added. This framework can and does allow the product, test and manufacturing engineers to benefit from hidden treasures.

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The need for continual quality improvement in semiconductor manufacturing processes is driven by customer demands for improved reliability, particularly in the automotive sector. However, Early Life Failures represent a unique challenge because although they pass all the ‘in line’ manufacturing checks, they subsequently fail in the customer application.

One approach to identifying and removing this class of device is to look for abnormalities (outliers) in the Bin 1 (good) population. EWS data is particularly suitable for this type of analysis because ‘part’ identities are preserved allowing subsequent device removal.

Analysis of parametric test results to identify atypical devices is a well-established form of outlier detection. Last year our presentation to the SWTW focused on the dynamic selection of outlier detection algorithms based on the characteristics of each test data population. Traditionally, these algorithms are based on statistical models, that focus exclusively on the numeric data values and therefore fail to take account of the additional information available in test data, in particular the test limits. This year we propose to present the implementation of outlier detection algorithms that dynamically scale their thresholds based on the proximity of the test limits to the main data population. The principal benefits of this approach are improved outlier detection sensitivity and the capability to classify outlier results based on their magnitude, with greater weight assigned to devices that are closer to the test limits.

A further benefit of performing analysis at EWS is the opportunity to apply geographical or spatial outlier detection, also know as ‘good die in a bad neighborhood’. This technique examines the bin results of the dice in the immediate vicinity of every good die. If a significant number of these devices are failures, then it can be argued that even though the die in question has passed the test program, it may well be at risk of failing at some point in the future and should therefore be eliminated. A number of enhancements to this basic technique will also be presented. For instance, certain test failures may be known predictors of reliability problems, by specifying which fail bins should be used for geographic analysis only these tests need be taken into consideration. Alternatively, the identification of step and repeat pattern failures across a wafer can also refine the process of geographic outlier detection by choosing to either include or exclude these failures.

Finally, to be an effective production tool, this type of analysis needs to be applied to all parametric tests on all the die on all the wafers being tested. This requires that the outlier detection system is fully automated in both analysis and reporting. To achieve this, the system needs to interface with existing factory automation systems, and product specific recipes tailor the analysis of the system to the individual requirements of each product. Once the analysis is completed the results are reported graphically or automatically merged with the original prober ink map.

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As device geometries continue to shrink and circuit complexity increases, the volume of parametric EWS data is increasing exponentially. With this trend, the ability to analyze and draw meaningful conclusions from this information is becoming increasingly important. The application of Outlier Detection to test data analysis is a powerful technique that can be used to assist in the pursuit of this goal.

One of the key applications of outlier detection is quality improvement. A strong link between Early Life Failures and devices that exhibit abnormal test results has been established. Thus by identifying and removing bin 1 (good) devices that exhibit abnormal performance in comparison to their peer population, the level of customer returns (DPPM) can be significantly reduced (improved). However, in order to achieve outlier removal for quality improvement, it is necessary to be able to identify the specific part in question. At wafer probe, each device can be easily identified by its x, y, co-ordinates and thus presents an ideal opportunity for outlier identification and removal.

Test program optimization can also benefit from the identification of outliers within parametric test results. When looking for correlations between tests, a pre-requisite for test removal, the presence of outliers can lead to erroneous results, either generating false correlations or false miscorrelations, making test removal candidates much harder to identify. The identification of outliers can also be used to highlight tests that have poor capability due to the presence of outliers, such tests must be retained in the test program to avoid shipping defective product to the customer.

However, it is important to recognise that different tests will generate different population distributions. For instance an Iddq test will typically display a Poisson or LogNormal characteristic, whereas an output voltage measurement could have a normal or perhaps a Bi-Modal distribution. Clearly, it is inappropriate to use the same outlier detection algorithms for such different data populations. This problem has been recognised for some time and a variety of different methodologies have been developed, each one addressing a particular population distribution. With an understanding of the data populations to be analysed, it is possible to select the most appropriate outlier detection algorithm for any given situation.

This approach is satisfactory for manual analysis of data, but has limitations when attempting to perform automated analysis. Although it is possible to pre-screen the test data in order to identify the particular type of distribution for each data set this is both time consuming and does not allow for the possibility that for a given test, the population distribution may change from wafer to wafer, possibly due to manufacturing variations.

To address these problems, a dynamic outlier algorithm selection methodology has been developed. By using various descriptive statistics, such as the mean, standard deviation and percentiles, it is possible to differentiate between differing data populations and thus make the automatic selection of outlier algorithm based on the current data rather than historical information. This approach offers a significant improvement in outlier detection (identification) coverage and hence the benefits that can be achieved.

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Quality improvement through DPPM (Defective Parts Per Million) reduction is an established approach for reducing the overall production costs of a product. In particular the identification and removal of ELF’s (Early Life Failures) is a key component in this strategy. However, conventional techniques for the identification and removal of ELF’s are expensive and therefore tend to be confined to high value, high reliability devices. Recent studies have confirmed a link between devices with abnormal results in their parametric test measurements (Outliers) and ELF’s. This has created the opportunity for a cost effective and generalized solution for the identification of ELF’s and thus the reduction of DPPM.

This paper outlines three outlier detection algorithms (Inter-Quartile Range, Part Average Testing and Median of Absolute Deviations) that can be used to identify outlier test results, before moving on to look at wafer level effects and circumstances where an abnormal test result may be ‘hidden’ within the main distribution of the data population.

Finally a practical production outlier detection system is described with particular attention focused on the implications for the data processing, data analysis and automation requirements.

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